光谱成像技术研究室知识库

High-resolution original video image acquisition has higher and higher requirements for data caching. How to perform real-time, high-speed, complete and effective caching of large-capacity data has become the focus of high-speed image data collection. This article will introduce the FPGA, which is produced by Xilinx, as the main control unit for data storage and processing, supplemented by an experimental platform built by other peripheral circuits. On this experimental platform, the performance of DDR SDRAM in high-speed image data acquisition is studied. Firstly, it introduces the block diagram of the high-speed image data transmission system, the principle of data acquisition subsystem and DDR SDRAM, and the basic principle of high-speed image data read and write control. In addition, the DDR SDRAM read and write data stream speed and bus occupancy rate are simulated and tested during high-speed image data acquisition. Finally, through a lot of experiments, the bandwidth utilization rate of the DDR SDRAM is up to 41.5% when the clock frequency of the DDR SDRAM is 200MHz, which improves the operating speed of the image data acquisition system and reduces the power consumption of the system. © 2019 SPIE.