A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS

doi:10.1109/LSSC.2024.3351683

OPT OpenIR > 瞬态光学研究室

	A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS
	Ma, Shuaizhe 1; Yin, Zhenyu 1; Ran, Nianquan 1; Xia, Yifei 1; Yang, Ruixuan 1; Yu, Chuanhao 1; Xu, Songqin 1; Wang, Binhao 2; Qi, Nan 3; Zhang, Bing 1; Shi, Jingbo 4; Gui, Xiaoyan 1; Geng, Li 1; Li, Dan 1
作者部门	瞬态光学研究室
	2024
发表期刊	IEEE Solid-State Circuits Letters
ISSN	25739603
卷号	7 页码:50-53
产权排序	2
摘要	This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB Ω, while showing an acrlong IRN current density of 10.4 pA/ √ Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mVpp, diff. The chip consumes power of 56 mW from 1.4 and 1.1-V supply. © 2018 IEEE.
关键词	100-Gb/s PAM-4 CMOS linearity low noise transimpedance amplifier (TIA)
DOI	10.1109/LSSC.2024.3351683
收录类别	EI
语种	英语
出版者	Institute of Electrical and Electronics Engineers Inc.
EI入藏号	20240315388252
引用统计
文献类型	期刊论文
条目标识符	http://ir.opt.ac.cn/handle/181661/97158
专题	瞬态光学研究室
通讯作者	Li, Dan
作者单位	1.Xi'an Jiaotong University, Faculty of Electronic and Information Engineering, Xi'an; 710000, China; 2.Institute of Optics and Precision Mechanics, University of Chinese Academy of Sciences, Xi'an; 710119, China; 3.Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing; 100083, China; 4.Beijing University of Posts and Telecommunications, State Key Laboratory of Information Photonics and Optical Communications, School of Integrated Circuits, Beijing; 100876, China
推荐引用方式 GB/T 7714	Ma, Shuaizhe,Yin, Zhenyu,Ran, Nianquan,et al. A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS[J]. IEEE Solid-State Circuits Letters,2024,7:50-53.
APA	Ma, Shuaizhe.,Yin, Zhenyu.,Ran, Nianquan.,Xia, Yifei.,Yang, Ruixuan.,...&Li, Dan.(2024).A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS.IEEE Solid-State Circuits Letters,7,50-53.
MLA	Ma, Shuaizhe,et al."A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS".IEEE Solid-State Circuits Letters 7(2024):50-53.

条目包含的文件
文件名称/大小	文献类型	版本类型	开放类型	使用许可
A 85-Gb s PAM-4 TIA （3170KB）	期刊论文	出版稿	限制开放	CC BY-NC-SA	请求全文